/*
 * (C) Copyright 2010
 * NVIDIA Corporation <www.nvidia.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _TEGRA2_H_
#define _TEGRA2_H_

#ifndef _MK_SHIFT_CONST
  #define _MK_SHIFT_CONST(_constant_) _constant_
#endif
#ifndef _MK_MASK_CONST
  #define _MK_MASK_CONST(_constant_) _constant_
#endif
#ifndef _MK_ENUM_CONST
  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
#endif
#ifndef _MK_ADDR_CONST
  #define _MK_ADDR_CONST(_constant_) _constant_
#endif

/* ap20/arclk_rst.h */
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0           _MK_ADDR_CONST(0x4)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0        _MK_ADDR_CONST(0x178)
#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0           _MK_ADDR_CONST(0x300)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0           _MK_ADDR_CONST(0x10)
#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0           _MK_ADDR_CONST(0x304)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0        _MK_ADDR_CONST(0x1c0)
#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0           _MK_ADDR_CONST(0x310)
#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0           _MK_ADDR_CONST(0x330)
#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0           _MK_ADDR_CONST(0x314)

#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0         _MK_ADDR_CONST(0x124)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0      _MK_ADDR_CONST(0x128)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0         _MK_ADDR_CONST(0x198)
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0         _MK_ADDR_CONST(0x1b8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_CLK_M _MK_ENUM_CONST(3)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0      _MK_ADDR_CONST(0x160)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0       _MK_ADDR_CONST(0x164)
#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0          _MK_ADDR_CONST(0x1c8)
#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0          _MK_ADDR_CONST(0x1d0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0         _MK_ADDR_CONST(0x114)
#define CLK_RST_CONTROLLER_PLLC_BASE_0               _MK_ADDR_CONST(0x80)
#define CLK_RST_CONTROLLER_PLLC_MISC_0               _MK_ADDR_CONST(0x8c)
#define CLK_RST_CONTROLLER_PLLM_BASE_0               _MK_ADDR_CONST(0x90)
#define CLK_RST_CONTROLLER_PLLM_MISC_0               _MK_ADDR_CONST(0x9c)
#define CLK_RST_CONTROLLER_PLLU_BASE_0               _MK_ADDR_CONST(0xc0)
#define CLK_RST_CONTROLLER_PLLU_MISC_0               _MK_ADDR_CONST(0xcc)
#define CLK_RST_CONTROLLER_PLLP_BASE_0               _MK_ADDR_CONST(0xa0)
#define CLK_RST_CONTROLLER_PLLP_MISC_0               _MK_ADDR_CONST(0xac)
#define CLK_RST_CONTROLLER_PLLX_BASE_0               _MK_ADDR_CONST(0xe0)
#define CLK_RST_CONTROLLER_PLLX_MISC_0               _MK_ADDR_CONST(0xe4)
#define CLK_RST_CONTROLLER_OSC_CTRL_0                _MK_ADDR_CONST(0x50)
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLP_OUT0 _MK_ENUM_CONST(0)

#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SHIFT _MK_SHIFT_CONST(3)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_SHIFT _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SHIFT _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SHIFT _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SHIFT  _MK_SHIFT_CONST(4)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SHIFT  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SHIFT _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SHIFT _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SHIFT _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SHIFT _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SHIFT _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SHIFT _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SHIFT  _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_SHIFT _MK_SHIFT_CONST(27)

#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SHIFT  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SHIFT  _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SHIFT _MK_SHIFT_CONST(12)
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SHIFT _MK_SHIFT_CONST(13)
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_SHIFT _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SHIFT _MK_SHIFT_CONST(6)
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SHIFT _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SHIFT  _MK_SHIFT_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SHIFT  _MK_SHIFT_CONST(25)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SHIFT _MK_SHIFT_CONST(30)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SHIFT _MK_SHIFT_CONST(31)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SHIFT _MK_SHIFT_CONST(11)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SHIFT  _MK_SHIFT_CONST(29)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SHIFT _MK_SHIFT_CONST(2)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SHIFT _MK_SHIFT_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SHIFT _MK_SHIFT_CONST(10)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_SHIFT _MK_SHIFT_CONST(27)

#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SHIFT _MK_SHIFT_CONST(15)
#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SHIFT _MK_SHIFT_CONST(22)
#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_SHIFT _MK_SHIFT_CONST(3)

#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_RANGE  31:31
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_ENABLE _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DISABLE  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_RANGE  30:30
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_RANGE 31:30
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_RANGE 15:0
#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RUN _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RANGE 31:28
#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_RANGE 6:4
#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0 _MK_ADDR_CONST(0x28)
#define CLK_RST_CONTROLLER_PLLP_OUTB_0         _MK_ADDR_CONST(0xa8)
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_RANGE 31:24
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_RANGE 18:18
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_ENABLE _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RUN _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RANGE 31:28
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_RANGE 7:4
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0  _MK_ADDR_CONST(0x20)
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_ENABLE _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_RANGE 31:31
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_RANGE 15:8
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_RANGE   7:0
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0  _MK_ADDR_CONST(0x24)
#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0     _MK_ADDR_CONST(0x30)
#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_RANGE                5:4
#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_RANGE                1:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0      _MK_ADDR_CONST(0x19c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_RANGE          31:30
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_RANGE       7:0
#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT4 _MK_ENUM_CONST(2)
#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_RANGE                 11:8
#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_VAL         _MK_MASK_CONST(0x10c)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_ENABLE  _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_RANGE                30:30
#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_RANGE                    31:30
#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_RANGE                 11:8
#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_RANGE                 7:4
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_RANGE                  4:0
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_RANGE                  17:8
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_RANGE              20:20
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DISABLE   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_RANGE                31:31
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_ENABLE    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_RANGE                30:30
#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_RANGE                 11:8
#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_RANGE                 7:4
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_RANGE                  22:20
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_RANGE                  4:0
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_RANGE                  17:8
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DISABLE   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_RANGE                31:31
#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_ENABLE    _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0                  _MK_ADDR_CONST(0x19c)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_RANGE        25:25
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_ENABLE _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_RANGE        24:24
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_ENABLE _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DISABLE _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DISABLE _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_RANGE              7:7
#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_RANGE              3:3
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0                       _MK_ADDR_CONST(0x58)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_ENABLE _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_RANGE       31:31
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_RANGE          3:0
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0              _MK_ADDR_CONST(0x5c)
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_RANGE 31:31
#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_RANGE  15:0
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_RANGE                 30:30
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_RANGE                 11:8
#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_RANGE                 7:4
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_RANGE                  17:8
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_RANGE                        31:31
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_RANGE                  27:27
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_RANGE                  22:20
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_RANGE                  4:0
#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_RANGE                      1:1
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_RANGE                      13:13
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_RANGE                       5:5
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0                  _MK_ADDR_CONST(0x340)
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_RANGE                      12:12
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_RANGE                       4:4
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_RANGE                    0:0
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_ENABLE                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_RANGE                      0:0
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_RANGE                      12:12
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_RANGE                       4:4
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0                  _MK_ADDR_CONST(0x344)
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DISABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEVICES_U_0                      _MK_ADDR_CONST(0xc)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0                      _MK_ADDR_CONST(0x18)
#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_RANGE                  9:9
#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_RANGE                  9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_ENABLE                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_ENABLE                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_RANGE                       31:30
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_RANGE                   7:0
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0                   _MK_ADDR_CONST(0x1d4)
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_RANGE                  27:27
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_RANGE                  26:26
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_RANGE                  25:25
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_RANGE                  24:24
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLX_OUT0                     _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_RANGE                 15:12
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLX_OUT0                     _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_RANGE                 11:8
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLX_OUT0                     _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLX_OUT0                    _MK_ENUM_CONST(8)
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_RANGE                        3:0
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_RANGE                       27:27
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_RANGE                       26:26
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_RANGE                       25:25
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_RANGE                       24:24
#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0                      _MK_ADDR_CONST(0x4c)
#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_RANGE                   9:9
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_RANGE                    0:0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_ENABLE                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_RANGE                   8:8
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_RANGE                  28:28
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_RANGE                  27:27
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_RANGE                  22:20
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_RANGE                  17:8
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_RANGE                  4:0
#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_RANGE                    31:24
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_RANGE                  18:18
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_RANGE                    17:17
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RANGE                     16:16
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_RANGE                  2:2
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_RANGE                    1:1
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLLP_OUTA_0                  _MK_ADDR_CONST(0xa4)
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_RANGE                    17:17
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RANGE                     16:16
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_RANGE                    15:8
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_RANGE                  2:2
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_RANGE                    1:1
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RANGE                     0:0
#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_RANGE                   29:27
#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_RANGE                   22:22
#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_RANGE                        3:0
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_RANGE                       29:29
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_RANGE                  27:27
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_RANGE                      24:24
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_DEFAULT                     _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_RANGE                       23:23
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_DEFAULT                      _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_RANGE                        22:22
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_DEFAULT                       _MK_MASK_CONST(0x0)
#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_RANGE                 21:21
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_RANGE                  6:6
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_ENABLE                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_RANGE                  6:6
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_ENABLE                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_RANGE                       31:30
#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_RANGE                  1:1
#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_ENABLE                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_RANGE                  1:1
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_ENABLE                 _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_RANGE                       31:30
#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_DISABLE                        _MK_ENUM_CONST(0)
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_ENABLE                   _MK_ENUM_CONST(1)
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_RANGE                    31:31
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_RANGE                       15:8
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_RANGE                        7:0
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0                 _MK_ADDR_CONST(0x2c)
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DISABLE                  _MK_ENUM_CONST(0)

/* ap20/arevp.h */
#define EVP_CPU_RESET_VECTOR_0                  _MK_ADDR_CONST(0x100)

/* ap20/arapb_misc.h */
#define APB_MISC_PP_TRISTATE_REG_A_0                 _MK_ADDR_CONST(0x14)
#define APB_MISC_PP_PIN_MUX_CTL_A_0                  _MK_ADDR_CONST(0x80)
#define APB_MISC_PP_PIN_MUX_CTL_B_0                  _MK_ADDR_CONST(0x84)
#define APB_MISC_PP_PIN_MUX_CTL_C_0                  _MK_ADDR_CONST(0x88)
#define APB_MISC_GP_ATCFG1PADCTRL_0                  _MK_ADDR_CONST(0x870)
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_ATCFG2PADCTRL_0                  _MK_ADDR_CONST(0x874)
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_DAP2CFGPADCTRL_0                 _MK_ADDR_CONST(0x888)
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_RANGE     16:12
#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_RANGE     24:20
#define APB_MISC_GP_DAP4CFGPADCTRL_0                 _MK_ADDR_CONST(0x890)
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_RANGE     16:12
#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_RANGE     24:20
#define APB_MISC_GP_GMBCFGPADCTRL_0                  _MK_ADDR_CONST(0x8f8)
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_GMCCFGPADCTRL_0                  _MK_ADDR_CONST(0x8fc)
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_GMDCFGPADCTRL_0                  _MK_ADDR_CONST(0x900)
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_SPICFGPADCTRL_0                     _MK_ADDR_CONST(0x8a8)
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_DBGCFGPADCTRL_0                     _MK_ADDR_CONST(0x894)
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_UART2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b4)
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_RANGE   16:12
#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_RANGE   24:20
#define APB_MISC_GP_UART3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b8)
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_RANGE   16:12
#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_RANGE   24:20
#define APB_MISC_GP_AOCFG2PADCTRL_0                     _MK_ADDR_CONST(0x86c)
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_GMACFGPADCTRL_0                     _MK_ADDR_CONST(0x8f4)
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_DAP1CFGPADCTRL_0                    _MK_ADDR_CONST(0x884)
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_RANGE     16:12
#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_RANGE     24:20
#define APB_MISC_GP_GMECFGPADCTRL_0                     _MK_ADDR_CONST(0x904)
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_RANGE       24:20
#define APB_MISC_GP_AOCFG1PADCTRL_0                     _MK_ADDR_CONST(0x868)
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_RANGE       16:12
#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_RANGE       24:20

#define APB_MISC_PP_TRISTATE_REG_B_0                    _MK_ADDR_CONST(0x18)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SHIFT        _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SHIFT       _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SFLASH       _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SHIFT         _MK_SHIFT_CONST(29)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SHIFT        _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SFLASH       _MK_ENUM_CONST(3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT        _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SDIO4        _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT         _MK_SHIFT_CONST(3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT        _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SDIO4        _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SHIFT         _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0                      _MK_ADDR_CONST(0x8c)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SHIFT        _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SDIO4        _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT         _MK_SHIFT_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT        _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SDIO4        _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SHIFT         _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SHIFT        _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SDIO4        _MK_ENUM_CONST(3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND         _MK_ENUM_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT         _MK_SHIFT_CONST(25)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT        _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND         _MK_ENUM_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT         _MK_SHIFT_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT        _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT         _MK_SHIFT_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND         _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND         _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_NAND         _MK_ENUM_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT        _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT       _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_NAND        _MK_ENUM_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT        _MK_SHIFT_CONST(21)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT       _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_NAND        _MK_ENUM_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT        _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT       _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_NAND        _MK_ENUM_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_D_0                    _MK_ADDR_CONST(0x20)
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT        _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_G_0                     _MK_ADDR_CONST(0x98)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT      _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_NAND       _MK_ENUM_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT       _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT      _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_NAND       _MK_ENUM_CONST(1)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT       _MK_SHIFT_CONST(27)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT      _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_NAND         _MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT               _MK_SHIFT_CONST(7)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT              _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_GMI                _MK_ENUM_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SHIFT                _MK_SHIFT_CONST(29)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SHIFT               _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_DEFAULT_MASK        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_GMI_INT             _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT               _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT              _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_GMI                _MK_ENUM_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT               _MK_SHIFT_CONST(8)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT              _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_GMI                _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT               _MK_SHIFT_CONST(10)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT              _MK_SHIFT_CONST(30)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_GMI                _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT               _MK_SHIFT_CONST(11)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT              _MK_SHIFT_CONST(28)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_GMI                _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT               _MK_SHIFT_CONST(12)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT              _MK_SHIFT_CONST(26)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_GMI                _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT               _MK_SHIFT_CONST(13)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT              _MK_SHIFT_CONST(24)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_GMI                _MK_ENUM_CONST(3)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT               _MK_SHIFT_CONST(14)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT              _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_GMI                _MK_ENUM_CONST(3)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT               _MK_SHIFT_CONST(20)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_GMI                _MK_ENUM_CONST(2)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT              _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT               _MK_SHIFT_CONST(19)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT              _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT_MASK       _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_GMI                _MK_ENUM_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT                _MK_SHIFT_CONST(22)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT               _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT_MASK        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT                _MK_SHIFT_CONST(23)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT               _MK_SHIFT_CONST(18)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT_MASK        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT                _MK_SHIFT_CONST(16)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT               _MK_SHIFT_CONST(4)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT_MASK        _MK_MASK_CONST(0x3)
#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_GMI                 _MK_ENUM_CONST(2)
#define APB_MISC_GP_HIDREV_0                    _MK_ADDR_CONST(0x804)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RANGE                      19:18
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTA                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_RANGE                       20:20
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RANGE                      17:16
#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTA                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_RANGE                       19:19
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_NORMAL                      _MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_RANGE                       3:2
#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_UARTD                       _MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_RANGE                        29:29
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_NORMAL                       _MK_ENUM_CONST(0)

/* ap20/aruart.h */
#define UART_LSR_0_THRE_SHIFT                   _MK_SHIFT_CONST(5)
#define UART_LSR_0_THRE_FIELD                   (_MK_MASK_CONST(0x1) << UART_LSR_0_THRE_SHIFT)
#define UART_LSR_0_RDR_SHIFT                    _MK_SHIFT_CONST(0)
#define UART_LSR_0_RDR_FIELD                    (_MK_MASK_CONST(0x1) << UART_LSR_0_RDR_SHIFT)
#define UART_THR_DLAB_0_0                       _MK_ADDR_CONST(0x0)
#define UART_IER_DLAB_0_0                       _MK_ADDR_CONST(0x4)
#define UART_IIR_FCR_0                  _MK_ADDR_CONST(0x8)
#define UART_LCR_0                      _MK_ADDR_CONST(0xc)
#define UART_MCR_0                      _MK_ADDR_CONST(0x10)
#define UART_LSR_0                      _MK_ADDR_CONST(0x14)
#define UART_MSR_0                      _MK_ADDR_CONST(0x18)
#define UART_SPR_0                      _MK_ADDR_CONST(0x1c)
#define UART_IRDA_CSR_0                 _MK_ADDR_CONST(0x20)
#define UART_ASR_0                      _MK_ADDR_CONST(0x3c)

/* ap20/arapbpm.h */
#define APBDEV_PMC_SCRATCH1_0                   _MK_ADDR_CONST(0x54)
#define APBDEV_PMC_SCRATCH20_0                  _MK_ADDR_CONST(0xa0)
#define APBDEV_PMC_SCRATCH23_0                  _MK_ADDR_CONST(0xac)
#define APBDEV_PMC_CNTRL_0                           _MK_ADDR_CONST(0x0)
#define APBDEV_PMC_CNTRL_0_MAIN_RST_RANGE            4:4
#define APBDEV_PMC_CNTRL_0_MAIN_RST_ENABLE           _MK_ENUM_CONST(1)
#define APBDEV_PMC_DPD_SAMPLE_0                      _MK_ADDR_CONST(0x20)
#define APBDEV_PMC_DPD_SAMPLE_0_ON_RANGE             0:0
#define APBDEV_PMC_DPD_SAMPLE_0_ON_DISABLE           _MK_ENUM_CONST(0)
#define APBDEV_PMC_DPD_ENABLE_0                      _MK_ADDR_CONST(0x24)
#define APBDEV_PMC_DPD_ENABLE_0_ON_RANGE             0:0
#define APBDEV_PMC_DPD_ENABLE_0_ON_DISABLE           _MK_ENUM_CONST(0)

#define APBDEV_PMC_PWRGATE_STATUS_0                     _MK_ADDR_CONST(0x38)
#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_RANGE                   0:0
#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_ENABLE                     _MK_ENUM_CONST(1)
#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_RANGE                      0:0
#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0                        _MK_ADDR_CONST(0x34)
#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_CP                   _MK_ENUM_CONST(0)
#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_RANGE                        2:0
#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_ENABLE                        _MK_ENUM_CONST(1)
#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_RANGE                 8:8
#define APBDEV_PMC_PWRGATE_TOGGLE_0                     _MK_ADDR_CONST(0x30)
#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_RANGE                   16:16
#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_ENABLE                  _MK_ENUM_CONST(1)

/* ap20/arfic_dist.h */
#define FIC_DIST_IC_TYPE_0                           _MK_ADDR_CONST(0x1004)
#define FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_RANGE     4:0
#define FIC_DIST_ENABLE_CLEAR_0_0                    _MK_ADDR_CONST(0x1180)

/* ap20/artimerur.h */
#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_RANGE       15:8
#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_RANGE        7:0
#define TIMERUS_CNTR_1US_0                           _MK_ADDR_CONST(0x0)
#define TIMERUS_USEC_CFG_0                           _MK_ADDR_CONST(0x4)

/* ap20/arflow_ctlr.h */
#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_RANGE                  7:0
#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP                 _MK_ENUM_CONST(2)
#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_RANGE                  31:29
#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_RANGE                  28:28
#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_RANGE                  25:25
#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_RANGE                  24:24

#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_RANGE                 11:11
#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_RANGE                 9:9
#define FLOW_CTLR_HALT_COP_EVENTS_0                     _MK_ADDR_CONST(0x4)
#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP                        _MK_ENUM_CONST(2)
#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_RANGE                 31:29

/* arcsite.h */
#define CSITE_CPUDBG0_LAR_0                     _MK_ADDR_CONST(0x10fb0)
#define CSITE_CPUDBG1_LAR_0                     _MK_ADDR_CONST(0x12fb0)

/* arpg.h */
#define PG_UP_TAG_0_PID_CPU                     _MK_ENUM_CONST(1431655765)    // // CPU aka "arm1" aka "mpcore" aka "arm11"
#define PG_UP_TAG_0                     _MK_ADDR_CONST(0x0)

/* arsdmmc.h */
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_RESETED _MK_ENUM_CONST(1)
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_RANGE   24:24
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0                     _MK_ADDR_CONST(0x2c)
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_RANGE 1:1
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_RANGE           2:2
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_DISABLE _MK_ENUM_CONST(0)
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_RANGE 15:8
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_ENABLE  _MK_ENUM_CONST(1)
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_RANGE                    19:16
#define SDMMC_POWER_CONTROL_HOST_0                      _MK_ADDR_CONST(0x28)
#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_RANGE                        1:1
#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_RANGE           5:5
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_RANGE                      31:16
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA4K _MK_ENUM_CONST(0)
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA8K _MK_ENUM_CONST(1)
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA16K _MK_ENUM_CONST(2)
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA32K _MK_ENUM_CONST(3)
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA64K _MK_ENUM_CONST(4)
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA128K _MK_ENUM_CONST(5)
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA256K _MK_ENUM_CONST(6)
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA512K _MK_ENUM_CONST(7)
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_RANGE       14:12
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_RANGE       11:0
#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0                  _MK_ADDR_CONST(0x4)
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_OSCILLATE                 _MK_ENUM_CONST(1)
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_RANGE   0:0
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV64                 _MK_ENUM_CONST(32)
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_RANGE 15:8
#define SDMMC_CAPABILITIES_0                    _MK_ADDR_CONST(0x40)
#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_RANGE           24:24
#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_RANGE     11:9
#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_RANGE           25:25
#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_V3_0    _MK_ENUM_CONST(6)
#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_V1_8    _MK_ENUM_CONST(5)
#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_POWER_ON         _MK_ENUM_CONST(1)
#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_POWER_OFF        _MK_ENUM_CONST(0)
#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_RANGE                   8:8
#define SDMMC_POWER_CONTROL_HOST_0                      _MK_ADDR_CONST(0x28)
#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_RANGE                   21:21
#define SDMMC_SYSTEM_ADDRESS_0                  _MK_ADDR_CONST(0x0)
#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_V3_3    _MK_ENUM_CONST(7)
#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_RANGE                 25:25
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_ENABLE  _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_RANGE           22:22
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_ENABLE      _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_RANGE               21:21
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_ENABLE  _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_RANGE           20:20
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_ENABLE _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_RANGE          19:19
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_ENABLE _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_RANGE        18:18
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_ENABLE     _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_RANGE          17:17
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_ENABLE _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_RANGE      16:16
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_ENABLE       _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_RANGE              7:7
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_ENABLE     _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_RANGE            6:6
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_ENABLE      _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_RANGE             3:3
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_ENABLE  _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_RANGE         1:1
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_ENABLE   _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_RANGE          0:0
#define SDMMC_INTERRUPT_STATUS_ENABLE_0                 _MK_ADDR_CONST(0x34)
#define SDMMC_RESPONSE_R0_R1_0                  _MK_ADDR_CONST(0x10)
#define SDMMC_RESPONSE_R2_R3_0                  _MK_ADDR_CONST(0x14)
#define SDMMC_RESPONSE_R4_R5_0                  _MK_ADDR_CONST(0x18)
#define SDMMC_RESPONSE_R6_R7_0                  _MK_ADDR_CONST(0x1c)
#define SDMMC_PRESENT_STATE_0                   _MK_ADDR_CONST(0x24)
#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_RANGE                 2:2
#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_RANGE                 1:1
#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_RANGE                 0:0
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_ERR            _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_RANGE           19:19
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_END_BIT_ERR_GENERATED _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_RANGE         18:18
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_CRC_ERR_GENERATED _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_RANGE             17:17
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_TIMEOUT  _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_RANGE         16:16
#define SDMMC_INTERRUPT_STATUS_0                        _MK_ADDR_CONST(0x30)
#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_RANGE                 0:0
#define SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_RANGE                  29:24
#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_ABORT                   _MK_ENUM_CONST(3)
#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_RANGE                   23:22
#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_NO_DATA_TRANSFER _MK_ENUM_CONST(0)
#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_RANGE            21:21
#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_ENABLE           _MK_ENUM_CONST(1)
#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_RANGE             20:20
#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_ENABLE             _MK_ENUM_CONST(1)
#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_RANGE               19:19
#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RESP_LENGTH_48BUSY _MK_ENUM_CONST(3)
#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RANGE               17:16
#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_WRITE        _MK_ENUM_CONST(0)
#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_RANGE               4:4
#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_DISABLE         _MK_ENUM_CONST(0)
#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_RANGE                  1:1
#define SDMMC_CMD_XFER_MODE_0_DMA_EN_DISABLE                 _MK_ENUM_CONST(0)
#define SDMMC_CMD_XFER_MODE_0_DMA_EN_RANGE                      0:0
#define SDMMC_INTERRUPT_STATUS_0                _MK_ADDR_CONST(0x30)
#define SDMMC_ARGUMENT_0                        _MK_ADDR_CONST(0x8)
#define SDMMC_CMD_XFER_MODE_0                   _MK_ADDR_CONST(0xc)
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_ERR                  _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_RANGE            19:19
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_END_BIT_ERR_GENERATED _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_RANGE          18:18
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_CRC_ERR_GENERATED _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_RANGE               17:17
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_TIMEOUT   _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_RANGE           16:16
#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_ERR          _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_RANGE              22:22
#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_ERR              _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_RANGE                  21:21
#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_TIMEOUT      _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_RANGE              20:20
#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_DEFAULT_MASK  _MK_MASK_CONST(0xf)
#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_RANGE               23:20
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_RESETED                       _MK_ENUM_CONST(1)
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_RANGE                 25:25
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_RESETED                       _MK_ENUM_CONST(1)
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_RANGE                 26:26
#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0xf)
#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_RANGE        23:20
#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_RESETED                       _MK_ENUM_CONST(1)
#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_NORMAL             _MK_ENUM_CONST(0)
#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_READ          _MK_ENUM_CONST(1)
#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_NO_RESPONSE    _MK_ENUM_CONST(0)
#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_DISABLE      _MK_ENUM_CONST(0)
#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_DISABLE        _MK_ENUM_CONST(0)
#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RESP_LENGTH_136 _MK_ENUM_CONST(1)
#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RESP_LENGTH_48 _MK_ENUM_CONST(2)
#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_GEN_INT  _MK_ENUM_CONST(1)
#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_RANGE           3:3
#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_RANGE           1:1
#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_RANGE         17:17
#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_RANGE             16:16
#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0                 _MK_ADDR_CONST(0x114)
#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0                 _MK_ADDR_CONST(0x118)
#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_DATA_TRANSFER  _MK_ENUM_CONST(1)
#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_ENABLE      _MK_ENUM_CONST(1)
#define SDMMC_CMD_XFER_MODE_0_DMA_EN_ENABLE              _MK_ENUM_CONST(1)
#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_ENABLE        _MK_ENUM_CONST(1)
#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_RANGE               1:1
#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ENABLE           _MK_ENUM_CONST(1)
#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_RANGE                   0:0
#define SDMMC_VENDOR_BOOT_CNTRL_0                       _MK_ADDR_CONST(0x110)
#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_DISABLE      _MK_ENUM_CONST(0)
#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_DISABLE          _MK_ENUM_CONST(0)
#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_RANGE         2:2

#define ARM_PERIPHBASE  0x50040000        
#define ARM_PERIPH_LEN  0x00002000        

#define NV_ADDRESS_MAP_SDRAM_BASE	0x00000000
#define NV_ADDRESS_MAP_PPSB_TMRUS_BASE	0x60005010
#define NV_ADDRESS_MAP_CLK_RST_BASE	0x60006000
#define NV_ADDRESS_MAP_CAR_BASE         NV_ADDRESS_MAP_CLK_RST_BASE
#define NV_ADDRESS_MAP_APB_MISC_BASE	0x70000000
#define NV_ADDRESS_MAP_APB_UARTA_BASE	(NV_ADDRESS_MAP_APB_MISC_BASE + 0x6000)
#define NV_ADDRESS_MAP_APB_UARTB_BASE	(NV_ADDRESS_MAP_APB_MISC_BASE + 0x6040)
#define NV_ADDRESS_MAP_APB_UARTC_BASE	(NV_ADDRESS_MAP_APB_MISC_BASE + 0x6200)
#define NV_ADDRESS_MAP_APB_UARTD_BASE	(NV_ADDRESS_MAP_APB_MISC_BASE + 0x6300)
#define NV_ADDRESS_MAP_APB_UARTE_BASE	(NV_ADDRESS_MAP_APB_MISC_BASE + 0x6400)
#define NV_ADDRESS_MAP_PMC_BASE		0x7000E400
#define NV_ADDRESS_MAP_DATAMEM_IRAM_D_LIMIT	0x4003FFFF
#define NV_ADDRESS_MAP_TMRUS_BASE		0x60005010

#define NV_ADDRESS_MAP_SDMMC1_BASE      0xC8000000
#define NV_ADDRESS_MAP_SDMMC2_BASE      0xC8000200
#define NV_ADDRESS_MAP_SDMMC3_BASE      0xC8000400
#define NV_ADDRESS_MAP_SDMMC4_BASE      0xC8000600

#define NV_ADDRESS_MAP_APB_DVC_BASE		0x7000D000
#define NV_ADDRESS_MAP_APB_I2C_BASE		0x7000C000
#define NV_ADDRESS_MAP_APB_I2C2_BASE		0x7000C400
#define NV_ADDRESS_MAP_APB_I2C3_BASE		0x7000C500

#define NV_ADDRESS_MAP_PPSB_CLK_RST_BASE	0x60006000

#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_RANGE			26:26
#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SW			_MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RANGE		15:14
#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_I2C			_MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RANGE		1:0
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_I2C2		_MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD1		_MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RANGE		9:8
#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_I2C		_MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RANGE		23:22
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_I2C2		_MK_ENUM_CONST(0)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_HDMI		_MK_ENUM_CONST(1)
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RANGE		31:30
#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_I2C3		_MK_ENUM_CONST(0)
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_RANGE		18:18
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_RANGE			25:25
#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_RANGE		24:24
#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_RANGE		31:31
#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_RANGE		12:12
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_ENABLE			_MK_ENUM_CONST(1)
#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_RANGE			1:11
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_RANGE			10:10
#define I2C_I2C_CNFG_0_PACKET_MODE_EN_GO			_MK_ENUM_CONST(1)
#define I2C_I2C_SL_CNFG_0_NEWSL_RANGE				2:2
#define I2C_I2C_SL_CNFG_0_NEWSL_ENABLE				_MK_ENUM_CONST(1)
#define I2C_IO_PACKET_HEADER_0_HDRSZ_RANGE			_MK_SHIFT_CONST(29):_MK_SHIFT_CONST(28)
#define I2C_IO_PACKET_HEADER_0_HDRSZ_ONE			_MK_ENUM_CONST(0)
#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RANGE			_MK_SHIFT_CONST(7):_MK_SHIFT_CONST(4)
#define I2C_IO_PACKET_HEADER_0_PROTOCOL_I2C			_MK_ENUM_CONST(1)
#define I2C_IO_PACKET_HEADER_0_PKTID_RANGE			_MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_RANGE		_MK_SHIFT_CONST(15):_MK_SHIFT_CONST(12)
#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_RANGE		_MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
#define I2C_IO_PACKET_HEADER_0_READ_RANGE			_MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
#define I2C_IO_PACKET_HEADER_0_READ_READ			_MK_ENUM_CONST(1)
#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_RANGE			1:1
#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SET			_MK_ENUM_CONST(1)
#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_RANGE			0:0
#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SET			_MK_ENUM_CONST(1)
#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE		7:4
#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_RANGE		3:0
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_RANGE	24:24
#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SET	_MK_ENUM_CONST(1)

#define DVC_CTRL_REG3_0					_MK_ADDR_CONST(0x8)
#define DVC_I2C_CNFG_0					_MK_ADDR_CONST(0x40)
#define DVC_I2C_TX_PACKET_FIFO_0			_MK_ADDR_CONST(0x60)
#define DVC_I2C_RX_FIFO_0				_MK_ADDR_CONST(0x64)
#define DVC_PACKET_TRANSFER_STATUS_0			_MK_ADDR_CONST(0x68)
#define DVC_FIFO_CONTROL_0				_MK_ADDR_CONST(0x6c)
#define DVC_FIFO_STATUS_0				_MK_ADDR_CONST(0x70)

#define I2C_I2C_CNFG_0					_MK_ADDR_CONST(0x0)
#define I2C_SL_CNFG_0					_MK_ADDR_CONST(0x20)
#define I2C_I2C_TX_PACKET_FIFO_0			_MK_ADDR_CONST(0x50)
#define I2C_I2C_RX_FIFO_0				_MK_ADDR_CONST(0x54)
#define I2C_PACKET_TRANSFER_STATUS_0			_MK_ADDR_CONST(0x58)
#define I2C_FIFO_CONTROL_0				_MK_ADDR_CONST(0x5c)
#define I2C_FIFO_STATUS_0				_MK_ADDR_CONST(0x60)

#define	NV_ADDRESS_MAP_PP_PIN_MUX_CTL_A			(NV_ADDRESS_MAP_APB_MISC_BASE + APB_MISC_PP_PIN_MUX_CTL_A_0)
#define	NV_ADDRESS_MAP_PP_PIN_MUX_CTL_C			(NV_ADDRESS_MAP_APB_MISC_BASE + APB_MISC_PP_PIN_MUX_CTL_C_0)
#define	NV_ADDRESS_MAP_PP_PIN_MUX_CTL_G			(NV_ADDRESS_MAP_APB_MISC_BASE + APB_MISC_PP_PIN_MUX_CTL_G_0)

#define	NV_ADDRESS_MAP_PP_TRISTATE_REG_A		(NV_ADDRESS_MAP_APB_MISC_BASE + APB_MISC_PP_TRISTATE_REG_A_0)
#define	NV_ADDRESS_MAP_PP_TRISTATE_REG_B		(NV_ADDRESS_MAP_APB_MISC_BASE + APB_MISC_PP_TRISTATE_REG_B_0)
#define	NV_ADDRESS_MAP_PP_TRISTATE_REG_D		(NV_ADDRESS_MAP_APB_MISC_BASE + APB_MISC_PP_TRISTATE_REG_D_0)

#define NV_ADDRESS_MAP_APB_CLR_RST_OSC_CTRL_REG		(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE + CLK_RST_CONTROLLER_OSC_CTRL_0)

#define NV_ADDRESS_MAP_APB_DVC_I2C_CNFG_REG		(NV_ADDRESS_MAP_APB_DVC_BASE + DVC_I2C_CNFG_0)
#define NV_ADDRESS_MAP_APB_I2C_CNFG_REG			(NV_ADDRESS_MAP_APB_I2C_BASE + I2C_I2C_CNFG_0)
#define NV_ADDRESS_MAP_APB_I2C2_CNFG_REG		(NV_ADDRESS_MAP_APB_I2C2_BASE + I2C_I2C_CNFG_0)
#define NV_ADDRESS_MAP_APB_I2C3_CNFG_REG		(NV_ADDRESS_MAP_APB_I2C3_BASE + I2C_I2C_CNFG_0)

#define NV_ADDRESS_MAP_APB_I2C_SL_CNFG_REG		(NV_ADDRESS_MAP_APB_I2C_BASE + I2C_SL_CNFG_0)
#define NV_ADDRESS_MAP_APB_I2C2_SL_CNFG_REG		(NV_ADDRESS_MAP_APB_I2C2_BASE + I2C_SL_CNFG_0)
#define NV_ADDRESS_MAP_APB_I2C3_SL_CNFG_REG		(NV_ADDRESS_MAP_APB_I2C3_BASE + I2C_SL_CNFG_0)

#define NV_ADDRESS_MAP_APB_DVC_I2C_TX_FIFO_REG		(NV_ADDRESS_MAP_APB_DVC_BASE + DVC_I2C_TX_PACKET_FIFO_0)
#define NV_ADDRESS_MAP_APB_I2C_TX_FIFO_REG		(NV_ADDRESS_MAP_APB_I2C_BASE + I2C_I2C_TX_PACKET_FIFO_0)
#define NV_ADDRESS_MAP_APB_I2C2_TX_FIFO_REG		(NV_ADDRESS_MAP_APB_I2C2_BASE + I2C_I2C_TX_PACKET_FIFO_0)
#define NV_ADDRESS_MAP_APB_I2C3_TX_FIFO_REG		(NV_ADDRESS_MAP_APB_I2C3_BASE + I2C_I2C_TX_PACKET_FIFO_0)

#define NV_ADDRESS_MAP_APB_DVC_I2C_RX_FIFO_REG		(NV_ADDRESS_MAP_APB_DVC_BASE + DVC_I2C_RX_FIFO_0)
#define NV_ADDRESS_MAP_APB_I2C_RX_FIFO_REG		(NV_ADDRESS_MAP_APB_I2C_BASE + I2C_I2C_RX_FIFO_0)
#define NV_ADDRESS_MAP_APB_I2C2_RX_FIFO_REG		(NV_ADDRESS_MAP_APB_I2C2_BASE + I2C_I2C_RX_FIFO_0)
#define NV_ADDRESS_MAP_APB_I2C3_RX_FIFO_REG		(NV_ADDRESS_MAP_APB_I2C3_BASE + I2C_I2C_RX_FIFO_0)

#define NV_ADDRESS_MAP_APB_DVC_I2C_PACKET_STATUS_REG	(NV_ADDRESS_MAP_APB_DVC_BASE + DVC_PACKET_TRANSFER_STATUS_0)
#define NV_ADDRESS_MAP_APB_I2C_PACKET_STATUS_REG	(NV_ADDRESS_MAP_APB_I2C_BASE + I2C_PACKET_TRANSFER_STATUS_0)
#define NV_ADDRESS_MAP_APB_I2C2_PACKET_STATUS_REG	(NV_ADDRESS_MAP_APB_I2C2_BASE + I2C_PACKET_TRANSFER_STATUS_0)
#define NV_ADDRESS_MAP_APB_I2C3_PACKET_STATUS_REG	(NV_ADDRESS_MAP_APB_I2C3_BASE + I2C_PACKET_TRANSFER_STATUS_0)

#define NV_ADDRESS_MAP_APB_DVC_I2C_FIFO_CONTROL_REG	(NV_ADDRESS_MAP_APB_DVC_BASE + DVC_FIFO_CONTROL_0)
#define NV_ADDRESS_MAP_APB_I2C_FIFO_CONTROL_REG		(NV_ADDRESS_MAP_APB_I2C_BASE + I2C_FIFO_CONTROL_0)
#define NV_ADDRESS_MAP_APB_I2C2_FIFO_CONTROL_REG	(NV_ADDRESS_MAP_APB_I2C2_BASE + I2C_FIFO_CONTROL_0)
#define NV_ADDRESS_MAP_APB_I2C3_FIFO_CONTROL_REG	(NV_ADDRESS_MAP_APB_I2C3_BASE + I2C_FIFO_CONTROL_0)

#define NV_ADDRESS_MAP_APB_DVC_I2C_FIFO_STATUS_REG	(NV_ADDRESS_MAP_APB_DVC_BASE + DVC_FIFO_STATUS_0)
#define NV_ADDRESS_MAP_APB_I2C_FIFO_STATUS_REG		(NV_ADDRESS_MAP_APB_I2C_BASE + I2C_FIFO_STATUS_0)
#define NV_ADDRESS_MAP_APB_I2C2_FIFO_STATUS_REG		(NV_ADDRESS_MAP_APB_I2C2_BASE + I2C_FIFO_STATUS_0)
#define NV_ADDRESS_MAP_APB_I2C3_FIFO_STATUS_REG		(NV_ADDRESS_MAP_APB_I2C3_BASE + I2C_FIFO_STATUS_0)

#define NV_ADDRESS_MAP_APB_DVC_CTRL_REG3		(NV_ADDRESS_MAP_APB_DVC_BASE + DVC_CTRL_REG3_0)

#define LOW_LEVEL_SRAM_STACK		0x4000FFFC

#ifndef __ASSEMBLY__
typedef volatile struct timerus {
        unsigned int cntr_1us;
} timerus_t;
#else  /* __ASSEMBLY__ */
#define PRM_RSTCTRL             0x7000E400
#endif

#define NAND_BASE               0x70008000
#define TEGRA2_SDRC_CS0         0x00000000

#define AP20_BOOT_INFO_BASE     0x40000000UL
#define AP20_PMC_BASE           0x7000e400UL

#endif
